【電磁技術(shù)在線】【EMC篇】- 6. PCB規(guī)則
講師：Longfei Bai
00：00 內(nèi)容介紹
01：50 信號完整性規(guī)則
02：50 電源完整性規(guī)則
04：00 EMC規(guī)則
06：15 boardcheck 工作流程
07：40 第一步：標(biāo)注線路
11：30 第二步：標(biāo)注元件
13：00 第三步：選擇規(guī)則
14：00 第四步：查看結(jié)果
21：10 違規(guī)報告
PCB layout need to follow design rules and pass the check (DRC). However, whether PCB can be fabricated and whether PCB will work after fabrication are the two different questions. The user can designate various nets and components that are critical for EMC, such as I/O nets, power/ground nets, and decoupling capacitors. To ensure the PCB work as we designed, we need to take the signals running on the PCB traces into account, and this requires more advanced design rules as explained in this video.
CST BOARDCHECK relieves the tedium and removes the human error by
examining each critical net in turn to check that it does not violate
any of the selected EMC or SI design rules. After the rule checking is
completed, the EMC rules’ violations can be viewed graphically or by report (new in 2021).
SI Rules
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[3] Differential Net Isolation
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[5] Differential Net Running Skew
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[13] Net Length
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[16] Net Stub
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[21] Routing between twoReference Planes
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[22] Single-Ended Net Isolation
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[23] Unconnected Via Pads
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[24] Via Clearance Overlap
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[25] Via Stub
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[26] Via to Net Coupling
PI Rules
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[1] Decoupling Capacitor Density
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[2] Decoupling Capacitor Distance to Via
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[9] IC Power/Ground Pin-Via Distance
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[10] Narrow Power/Ground Traces
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[17] Power/Ground Trace Decoupling
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[18] Power Net Overlapping
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[19] Power Pin Capacitor Distance
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[20] Power Via Density
EMC Rules
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[3] Differential Net Isolation
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[4] Differential Net Matching
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[6] Distance from Filter to Connector
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[7] Distance from Oscillator to Clock Driver
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[8] Exposed Trace Length
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[11] Net Changing Reference
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[12] Net Crossing Split
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[14] Net Near Connector Net
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[15] Net Near Edge of Reference
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[22] Single-Ended Net Isolation
